For over a decade, mixed signal CMOS processing technologies have been proposed as the ultimate solution for implementation of systems-on-chip solutions but multiple process modules continue to drive up process complexity and costs, especially when large amounts of DRAM is required in the design.
However, there are now alternatives as multi die packaging has also benefited from a decade of improvements and added new capabilities to include different components like crystals in the same package as RF silicon, DRAM and multi-processor ASIC – all in a single package!
So, can Advanced Packaging help you achieve your performance and cost goals at the shipment volumes you are projecting?
Please join us as Dave Danovitch, a Senior Engineer from IBM’s world class packaging facility in Bromont, Quebec describes next-generation packaging technology for the ultimate in high density pins, including: flip chip packaging, organic SiP’s and Thru Silicon Via (TSV) chip stacking.
We are still looking for a local company to describe their real world experiences from a user’s viewpoint. So, please contact Iain Scott at email@example.com or call (613) 797-8884 if you can help. The goal is for all participants to share their own company’s experiences to provide a note of real-world caution.
Please join us in Montréal to gain better insight into a complex subject and enjoy valuable networking time with your colleagues in an informal sharing of best industry practices.
So, register now to ensure your place at this valuable Best Practice Forum!